The present invention pertains in general to microchip processing and in particular to a thin wafer backgrinding operation.
The microelectronics industry is consistently achieving an ever shrinking size of devices and ever greater levels of device integration, resulting in higher interconnect densities. A steady succession of interconnect developments and strategies has evolved in the packaging industry to meet the demand of these high interconnect densities. Nearly all have been aimed at one goal, reduced size and with few exceptions, reduced size also translates into lower cost. Thus in state of the art packaging, dual-in-line packages have been largely replaced by surface mount packages, and newer developments, such as chip-on-chip (COC) and multichip modules (MCM), are meeting the high density interconnect demand. These and similar developments are directed toward reducing the package area, i.e. the x-y dimension of the package.
The issue of package thickness has been addressed by techniques for thinning the wafers from which the chips are singulated. The thinning operation is performed on fully processed wafers by mounting the wafer, processed side down, on a temporary carrier such as an adhesive tape and grinding the backside of the wafer. A variety of wafer thinning techniques have been proposed and used, ranging from machines providing simple mechanical abrasion using, e.g., an abrasive grinding wheel, to chemical etching and polishing techniques, and combinations of these, e.g. chemical mechanical polishing (CMP). In a typical wafer thinning process, a 200 mm diameter wafer of completed ICs may be reduced from an initial thickness of 26 to 30 mils to a final thickness of only 12 mils before it is remounted and diced.
The individual IC chips, or dies, are then packaged, which may involve assembly into an MCM or COC tile. The term tile as used herein refers to a sub-assembly of at least two components, a substrate and at least one active chip flip-chip bonded to the substrate. The substrate of the tile may or may not be an active chip. In a common arrangement, the tile comprises two or more components, a substrate, and one or more chips that can be alone, side-by-side, or chip-on-chip, and where the substrate may be active or passive. The chip-on-chip may comprise two stacked chips, or two or more chips stacked on one, usually larger, chip. The term substrate refers in this context to a support element, either active or passive, and the term chip typically refers to a fully processed, i.e. finished, semiconductor IC device. In the preferred case, all of the elements in the tile are semiconductor, typically silicon although the substrate may also be ceramic.
In the assembly operation, the singulated die are handled through a die mounting and bonding tool, and additional interconnections made as needed. To withstand this additional processing without fracture, a die thickness of 10 mils or greater is generally adequate. However, a die thickness of less than 8 mils, which would otherwise be desirable for many applications, is prohibited by the exposure to handling after thinning and by wafer warpage.
Wafer physical warpage is created by stresses that are inherent in the metal layers of the wafer. In addition, tapes that are placed onto the wafer to allow for processing can contribute to wafer warpage. This can be a result of unbalanced tape tension, tape material shrinkage, etc. in which these stresses are transferred to the wafer creating a distortion of the wafer such as bowing.
The limitation on thickness of the die applies also to a support wafer or substrate. This limitation, 10 mils or greater, is generally accepted in the industry as a norm, and tiles of less than 20 mils have not been attainable. This constraint rules out the use of stacked chips or tiles in several important applications, such as so-called smart cards, i.e. credit cards with imbedded chips.